This invention relates generally to semiconductor devices, and more particularly relates to synchronous semiconductor devices, i.e., semiconductor devices whose operation is coordinated by an externally-applied oscillating clock signal.
The field of semiconductor devices, including microprocessors, memory devices, digital signal processors, and the like, is enormously active and rapidly developing. Various categories and sub-categories of semiconductor devices are known and commercially available. The ever-increasing popularity and ubiquity of computers and computer-based devices, both in the consumer and industrial realms, is such that the demand for semiconductor devices of a variety of different types will continue to grow for the foreseeable future.
As a general proposition, semiconductor devices can be classified into one of two broad categories: synchronous and asynchronous. A synchronous semiconductor device is one whose operation is coordinated by or synchronized with a (typically) externally-applied clock signal; whereas an asynchronous device requires no clock signal.
One of the more common categories of semiconductor memory devices used today is the dynamic random access memory, or DRAM. Among the desirable characteristics of any DRAM are a high storage capacity per unit area of semiconductor die area, fast access speeds, low power consumption, and low cost.
One approach that has been used to optimize the desirable properties of DRAM has been to design such devices such that they are accessible synchronously. A synchronous DRAM typically requires an externally-applied clocking signal, as well as other externally-applied control signals whose timing must bear certain predetermined relationships with the clock signal. Likewise, digital data is read from and written to a synchronous memory device in a synchronous relationship to the externally-applied clock signal. Synchronous DRAM technologies have been under development for many years, and synchronous DRAM (frequently referred to as xe2x80x9cSDRAMxe2x80x9d) is used in a broad spectrum of commercial and industrial applications, including the personal computer industry.
Those of ordinary skill in the art will appreciate that, as the storage capacity of SDRAMs is increased, so too does the die size of the semiconductor substrate usually increase (notwithstanding concurrent improvements in semiconductor processing technologies allowing for higher-density memory storage per unit area). It is also recognized that as the substrate size increases, other factors affecting the overall synchronization of the electrical signals propagating throughout the substrate also come into play. Issues such as capacitive coupling, impedance loading, processing variation and the like can make it challenging to ensure that the interrelationship between the timing of separate signals conducted along and within the substrate remains synchronized. As the processing speed of a semiconductor device increases, such synchronization issues (sometimes referred to generally as xe2x80x9cskewxe2x80x9d) can become more and more critical. Timing differentials on the order of picoseconds can become determinative of whether a device will operate reliably and properly.
In typical implementations, the external clock signal CLK comprises a simple, periodic xe2x80x9csquarexe2x80x9d wave, such as shown in FIG. 3a, oscillating with reasonably uniform periodicity between a logical high voltage level (for example, 3.3 V) and a logical low level (typically 0 V) with a duty cycle of 50% (meaning that the signal is at a logical xe2x80x9chighxe2x80x9d level the same amount of time that it is at a logical xe2x80x9clowxe2x80x9d level during each complete clock cycle). In present state-of-the-art semiconductor devices, the clock signal may have a frequency on the order of hundreds of megahertz.
A synchronous semiconductor device such as an SDRAM will typically require an external input signal such as a clock signal to be provided to several (or even numerous) separate but interrelated functional subcircuits of the device. As a matter of ordinary semiconductor device layout, it is typical for each of the separate subcircuits of an overall device to be physically disposed at different and perhaps distributed locations throughout the substrate as a whole. This means that the conductive lengths, and hence such characteristics as capacitive and complex impedance loads of the various conductive traces which carry electrical signals throughout the substrate, will vary from signal to signal. Hence, for example, the propagation delay of a clock signal from a clock signal input pin to one functional subcircuit may be different than the propagation delay to another functional subcircuit; such differences can be critical for devices operating at very high clock rates, on the order of 100 MHz or so (and perhaps less).
To address such considerations, an approach referred to as xe2x80x9cdelay-locked loopxe2x80x9d or xe2x80x9cDLLxe2x80x9d can be employed. FIG. 1 is illustrative of a simple example of DLL implementation. In FIG. 1, an externally-applied clock signal CLK is applied to an input pin 12 of a hypothetical memory device 10. As shown in FIG. 1, the externally-applied CLK signal is applied to a DLL block 20. DLL block 20 operates to derive a plurality of separate internal clock signals which are then provided to the various subcircuits of memory device 10 on lines 22, 24, and 26. (Although only three internal clock signals are depicted in FIG. 1, those of ordinary skill will appreciate that more than three internal clock signals may be required in any given implementation.) The function of DLL block 20 (which may represent circuitry distributed throughout the area of the substrate, notwithstanding the centralized location represented for convenience in FIG. 1) is to adjust the relative timing of the clock signals provided on lines 22, 24, and 26 to the various distributed subcircuits of device 10 such that overall synchronous operation of the device 10 can be achieved.
DLL blocks such as DLL block 20 in FIG. 1 may utilize some type of loop-back operation, as represented by exemplary dashed line 28 in FIG. 1, whereby DLL block 20 is provided with feedback for comparing the timing of the clock signal supplied on line 22 to command block 14 with the timing of incoming external clock signal CLK.
In the simplified example of FIG. 1, since command input buffer 14 and data input buffer 16 each receive and operate based on a clock signal, the command (CMD) input pin 15 and data (DATA) input pin 17 are said to be synchronous inputs. As such, binary data applied to input pins 15 and 17 will only be stored in the respective buffers 14 and 16 (a process sometimes referred to as xe2x80x9csignal capturexe2x80x9d) upon a rising or falling edge of the corresponding internal clock signal.
As a result of the functionality of a typical DLL circuit such as DLL block 20 in FIG. 1, if the propagation and loading characteristics of line 22 varies significantly from that of, say, lines 24 and 26, DLL circuit can account for such differences in order to ensure that proper device operation can be maintained. Internally to DLL circuit 20, separate delays and skews (programmable, or automatically adjusted) may be introduced into the externally-applied clock signal to ensure that each of the other functional blocks in device 10 receives clock signals that are substantially synchronized with the others. The delays and skews introduced by a DLL may be miniscule, on the order of picoseconds, but may be nonetheless critical to the proper operation of a semiconductor device.
The functionality of DLLs can be thought of generally as a process of internal clock signal generation, and those of ordinary skill in the art will doubtless be familiar at least generally with the concept of DLLs in semiconductor devices. Various examples of DLL implementations for synchronous memory devices are proposed in U.S. Pat. No. 5,920,518 to Harrison et al., entitled xe2x80x9cSynchronous Clock Generator Including Delay-Locked Loop;xe2x80x9d U.S. Pat. No. 6,201,424B1 to Harrison, entitled xe2x80x9cSynchronous Clock Generator including a Delay-Locked Loop Signal-Loss Detector;xe2x80x9d and U.S. Pat. No. 6,130,856 to McLaury, entitled xe2x80x9cMethod and Apparatus for Multiple Latency Synchronous Dynamic Random Access Memory.xe2x80x9d The aforementioned ""518, ""424, and ""856 patents are each commonly assigned to the Assignee of the present invention and each are hereby incorporated by reference herein in their respective entireties.
Those of ordinary skill in the art will appreciate that DLLs are frequently implemented in a manner specific to an intended operational speed of a clocked semiconductor device. For example, an SDRAM (and its DLLs) may be designed with a specification that it be operated with a clock speed of, say 100 MHz. In such a case, operation of a device at a speed substantially different (either slower or faster) than its specified speed may result in a situation in which the ability of its internal DLL block(s) to maintain synchronization between internally generated clock signals and the externally-applied clock signal(s) may be compromised.
The inability to maintain synchronization among internally generated clock signals and an externally-applied clock signal is typically not problematic in the course of normal operation of a semiconductor device. One reason why such inability may become a problem, however, relates to the testing of semiconductor devices. In some cases, it may be necessary or desirable to conduct tests on a partially or fully fabricated device at an operational speed (i.e., clock speed) that is substantially different than the ultimately intended operation of the device(s) being tested.
DRAMs, including SDRAMs, are often incorporated into so-called xe2x80x9cmemory modulesxe2x80x9d comprising a plurality of individual memory devices mounted upon a printed circuit board. After DRAMs (comprising one or more discrete integrated circuit components) are packaged and mounted on a printed circuit board, testing of the individual memory circuits becomes problematic because of the inaccessibility to internal circuit nodes, such as those related to the DLL circuitry. One reason that this is problematic is that often, the dedicated testing appliances and fixtures used to test semiconductor devices such as memory are incapable of operating at the speeds for which the devices under test are specified to operate. Thus, it may be desirable and/or necessary to operate the device(s) under test at slower clock speeds than they would be in the course of xe2x80x9cnormalxe2x80x9d operation. As noted above, however, this can present problems in terms of the ability of certain internal circuitry, particularly DLLs, to function properly except within certain ranges of xe2x80x9cnormalxe2x80x9d operating frequencies.
One solution to this potential problem has been to provide a xe2x80x9cmode registerxe2x80x9d to which predetermined patterns of bits may be addressed to cause the device to begin operating in alternative modes, such as a test mode. In such an approach, decoder circuitry coupled to the mode register is conditioned to detect certain predetermined patterns of bits and to issue appropriate control signals and make appropriate internal adjustments to enable the device to operate a mode corresponding to the predetermined pattern of bits.
Operation in a test mode may involve temporarily disabling certain internal subcircuits, such as DLL circuitry, that might otherwise prohibit proper operation of the device at clock speeds substantially differing from the device""s xe2x80x9cnormalxe2x80x9d operating speed. Once the circuitry in question has been disabled, operation in a test mode (e.g., a mode involving a substantially slower operating speed) can commence without concern about such adverse effects.
One potential drawback to the above-described test mode-register approach is that the test mode circuits could impact speed-sensitive and critical circuit paths. That is, disablement of the circuitry known to be sensitive to substantial changes in operational speed could affect other timing relationships among internal signals. Another potential problem with the above-described approach is that providing a mode register may itself be undesirable, as it consumes valuable semiconductor xe2x80x9creal estatexe2x80x9d (i.e., substrate area) and increases circuit complexity. Even where an approach such as a mode register is employed, the number of different operational modes that can be specified is necessarily limited by the number of mode register bits, such that an insufficient number of modes may be available to accommodate all of the various test modes desired to be implemented.
Still another potential drawback to the xe2x80x9cmode registerxe2x80x9d approach to the challenge of specifying an alternative mode of operation of a semiconductor device is that a control or data signal xe2x80x9ccapturexe2x80x9d is required not only to place the device into the alternative mode, but also to restore the device to its xe2x80x9cnormalxe2x80x9d mode. Consider, for example, an implementation in which a command or data input port used to place a device into an alternative mode of operation relies upon a xe2x80x9ccapturexe2x80x9d subcircuit (such as command subcircuit 14 or data subcircuit 16 in the hypothetical example of FIG. 1) that itself depends upon a DLL-generated clock signal for proper operation. While it might be possible to place such a semiconductor device into the alternative mode of operation (assuming that it begins operating in a mode in which the DLL circuitry is activated), once the alternative mode of operation in which the DLL circuitry is deactivated is commenced, it might be difficult or impossible to thereafter xe2x80x9ccapturexe2x80x9d the command(s) or data necessary to restore the device to its xe2x80x9cnormalxe2x80x9d mode of operation. This is because the subcircuits used to capture the commands or data that might be used to restore xe2x80x9cnormalxe2x80x9d operation cannot be xe2x80x9ccapturedxe2x80x9d by the corresponding subcircuits so long as the DLL circuitry is deactivated. This is a xe2x80x9cCatch 22xe2x80x9d or xe2x80x9cchicken-and-eggxe2x80x9d situation, in which the very mechanism for allowing xe2x80x9cnormalxe2x80x9d operation of the device to resume is incapable of being reactivated until xe2x80x9cnormalxe2x80x9d operation resumes.
Thus, it is believed that there remains a need for an improved method and apparatus by which a subcircuit within an integrated circuit device can be temporarily powered-down or disabled, and subsequently restored to normal operation.
The present invention relates to an apparatus and corresponding method by which a semiconductor device having one or more DLL-reliant subcircuits may be placed into alternative modes of operation in which the DLL circuitry is temporarily deactivated, and thereafter restored to xe2x80x9cnormalxe2x80x9d operation (i.e. a mode in which the DLL circuitry is active).
In accordance with one embodiment, the invention relates to a method and apparatus in which one or more input signals that are normally accepted without involvement of internal DLL-reliant subcircuits (i.e., non-synchronous inputs) are additionally utilized to place a semiconductor device into an alternative mode of operation in which one or more internal DLL subcircuits are disabled.
In one embodiment, the present invention comprises a synchronous DRAM having one or more externally-applicable input signals which are received into internal circuitry by means not involving synchronization with an internally-generated DLL clock signal. In accordance with various conceivable embodiments of the invention, a combination of one or more externally-applied signals to a semiconductor device conditions the device to operate in a mode alternative to a xe2x80x9cnormalxe2x80x9d operating mode. Such alternative mode preferably (but not exclusively) comprises a mode in which the device, being a synchronous device responsive in a normal mode to operate in a given manner, is conditioned in the alternative mode to operate in the same given manner except at a lower or higher rate of synchronous speed, i.e., at a lower or higher clock rate relative to its normal mode.
In one embodiment, the present invention comprises a synchronous DRAM having a plurality of input pins adapted to receive signals in synchronization with one or more internally-generated clock signals derived from at least one externally-applied external clock signal, the one or more internally-generated clock signals being generally referred to as DLL (delay lock loop) signals. Additionally, the disclosed DRAM has at least one, and preferably two, input pins adapted to receive signals asynchronously with respect to any internally- or externally-generated clock signal, or which are adapted to receive signals either synchronously or asynchronously with respect to any internally- or externally-generated signals.
In one disclosed embodiment, the semiconductor device enables both the deactivation and activation of internal processes relating to the generation of synchronous signals. In a particular embodiment, the invention encompasses the disabling and subsequent enabling of an internal delay lock loop subcircuit that is adapted in normal operation to coordinate the generation of one or more internal clocking signals with the application of one or more eternally-applied clock signals. In accordance with one aspect of the invention, the deactivation and activation of the internal DLL subcircuit is accomplished by means of application of signals to the one or more input pins adapted in normal operation to receive signals asynchronously with respect to any internally- or externally-generated clock signals.
In one specifically disclosed embodiment, the invention involves the use of external xe2x80x9cresetxe2x80x9d and xe2x80x9cchip selectxe2x80x9d inputs to an SDRAM. In this particular embodiment, when an external xe2x80x9cresetxe2x80x9d signal is asserted upon an external input to the SDRAM with the externally-applied xe2x80x9cchip selectxe2x80x9d input is applied at a first logic level to another external input, the SDRAM is conditioned to operate in a xe2x80x9cnormalxe2x80x9d mode, but when the xe2x80x9cresetxe2x80x9d signal is asserted with the xe2x80x9cchip selectxe2x80x9d input being applied at a second logic level, the SDRAM is conditioned to operate in an alternative mode of operation in which certain delay lock loop (DLL) subcircuitry within the SDRAM is disabled. With the DLL subcircuitry disabled, the SDRAM is capable of operating in an otherwise normal mode of operation, but with a clock signal having a substantially different frequency than specified for its normal operation being supplied to its one or more clock signal inputs.